I. Field of the Invention
This invention relates, generally, to the field of semiconductor (IC) technology and to high density semiconductor chip packaging schemes on a board and, more particularly, relates to an improved chip-to-board connection assembly which can enable both high density integration as well as high-speed operation.
II. Description of the Prior Art
Conventional methods of chip attaching schemes, for example, wire bond or flip-chip, have some drawbacks for high density integration and high-speed systems application. Namely, inductance and uncontrolled impedance of bond wires compromises signal transmission integrity and, especially, at the high data rates. As multichip modules (MCMs) or sub-systems become more and more complex, the number of bond wires correspondingly grows. Such expansion in the number of bond wires can be in the thousands. The rise in cost resulting from this becomes an ever greater fraction of the overall assembly cost and, also, leads to a decrease in the reliability of the system.
Most high-performance semiconductor integrated circuit chips require power bypass capacitors which, due to the relatively large values required, cannot, practically, be integrated into the ICs and, therefore, are usually added to the MCM or board assembly. That is, such high value capacitors are installed on the board or MCM externally of the high-performance IC or semiconductor chip. This results in greater expense and in loss of available chip area on the board (e.g. MCM, circuit board [PCB], mounting board, wiring substrate, etc.) and, also, results in greater reliability risk exposure. In fact, even if such bypass capacitors can be integrated into the MCM, for example, this still represents an increase in both cost and reliability risk. This is because the manufacturer (OEM or vendor) must necessarily increase the number of process steps, for example, to provide additional layers to the MCM. Likewise, DC blocking capacitors, which may be necessary, can also represent a significant yield risk to the ICs and so these too would be assembled on the MCM or board thereby further adding to the cost and risk.
Correspondingly, with an increase in the complexity and/or cost of the board (or MCM) assembly, there is a corresponding increase in the need to be able to do rework on the assembly. That is, if a component of the connection assembly fails, the MCM assembly must facilitate the replacing of that component. Otherwise, the cost and schedule invested in the manufacture of the overall module will be lost.
IC mounting boards and, especially, high-speed digital circuit boards (e.g., high-performance MCMs) must provide solutions to separate, and sometimes incompatible, problems. For one, in order to maintain high bandwidth, interconnection of chips should be effected through controlled impedance paths and with few discontinuities. Also, latency and data skew concerns dictate -that these controlled impedance paths must be as short as possible. However, as operating speeds (e.g., chip clock rates) as well as semiconductor chip complexities increase, the power requirements of such chips correspondingly increase, which leads to a further requirement for an efficient thermal management to dissipate the heat being generated by this power. Thermal management requires a large portion of the chip surface to be in intimate contact with a good thermal conductor having sufficient thermal mass to remove the heat generated by the chip.
With regard to chip attaching schemes such as ones which employ wire bonds or ribbon bonds, efficient heat dissipation is afforded through the back or rear surface of the chip or die. This can be seen from FIG. 2 of the drawings which is illustrative of one such conventional approach of chip-on-board design for efficient thermal management. This illustration exemplifies efficient thermal management by placing the back side of the chip 21 in contact with a thermal conductor 22 which can be of any well-known conductive material (e.g., Cu metal or Cu--W metal alloy, etc.). Such a design scheme as that shown in FIG. 2 does provide for a separation of the electrical and thermal pads, with the purpose of optimizing the thermal management of the heat being dissipated by the chip. In this connection, the wirings on the board including the interconnection of the wire or ribbon bonds 24 are effected on the board dielectric and interconnect portions 23, which may have one or more wiring layers. 25 on chip 21 represents the bonding pads (or external terminal pads) of the chip.
The example shown in FIG. 2 and the like does provide for effective thermal management of heat dissipation associated with high-power/high-speed semiconductor chips. The method of interconnection used, however, typically has larger amounts of discontinuities than are desirable, requires additional area between chips leading to longer interconnect pads, and only allows the formation of I/O (input/output) bonding pads at the outer periphery of the chip, which leads to compromises in the electrical design. Such conventional approaches to chip-to-board attaching schemes leads to wire inductances and uncontrolled impedances of bond wires which compromises signal integrity, especially, at the high data transmission rates. This, of course, compromises the ability to increase the data transmission speed. Also, the ability to perform rework and repair is limited by the number of times wire bonding can be done to the pads on the board.
Pulling bond wires and the like can be arduous; tails can remain after the bond wires are pulled and wire lands or pads can be ruptured, all of which can greatly complicate the rework process. This would be compounded by the fact that a finished connection assembly (resulting from rework) is rarely as clean and robust as the original work and so reliability can suffer. An entire module may necessarily be scrapped even for the loss of a single wire land that happens to be too badly damaged in an attempt to replace a bond wire. Reference to a bond wire is strictly for discussion only. Such wiring can be any type of wire bonds or, for that matter, ribbon bonds or tape automated bonding (TAB). Increasing the number of times a chip can be replaced usually leads to compromises in the electrical design of the chip (pad size, number of pads, line spacing, etc.).
Flip-chip technology can solve some of the problems associated with signal integrity, assembly, and rework attributed to use of bond wires and the like for connecting the chip to the board (e.g., MCM). However, integrated circuit (IC) technologies that require a high bandwidth capability are known to consume a great deal of power and, therefore, generate a considerable amount of heat when operating. Such heat would be more effectively removed from the rear surface of such a high-power and/or high-speed chip (or die). That is, front side heat removal, which would be the case if the device is mounted as a flip-chip, is not a feasible option, for example, in high-speed devices such as GaAs ICs and the like due in part to the presence of air bridges, controlled impedance structures, and increased parasitic capacitance to the devices and their interconnect. When you have both high-power and high-speed requirements of IC chip construction, the process of forming wirings becomes quite troublesome and it becomes quite difficult to provide a flip-chip construction scheme.
Flip-chip technology is known to be an excellent way for achieving high bandwidth interconnection. FIG. 1 of the drawings shows comparisons of inductive discontinuities between various technologies. Lower lead inductance allows higher bandwidth signal transmission. Flip-chip technology also allows closer spacing of chips for more compact boards and with shorter interconnect paths between chips. Also, flip-chip mounting allows connection of all of the chip pads to the board or MCM in a single step, thereby increasing the reliability and lowering the cost of assembly. Furthermore, through the use of flip-chip technology, interconnections of chips are effected through controlled impedance paths and with few discontinuities, in contradistinction with that typically associated with conventional chip-to-board connection schemes such as wire or ribbon bonding and the like. However, IC technologies capable of high bandwidth are known to consume a lot of power and generate a considerable amount of heat which is most effectively taken out from the rear side of the die. As noted earlier, front side heat removal is not an option in high or very high-power devices and/or high-speed devices such as HBT (heterostructure bipolar transistor) devices, heterostructure FET devices, GaAs ICs, etc., and the like, when connected as flip-chips. Also, if the semiconductor chips on the MCM or board have both high-power and high-speed requirements, thereby generating a substantial amount of heat during operation, the propensity for wire problems would generally preclude a standard flip-chip mounting.
One method available for efficient thermal management and, at the same time, providing a high bandwidth interconnect network is to mount the chips on a thermal conductor (or heat sink) similarly as that shown in FIG. 2 of the drawings, and then deposit or apply the layers of dielectric and metal, for example, including through employing lithography processes to implement the high-speed controlled impedance interconnect. Although such a method has the advantage of separating the thermal paths from the electrical paths and thereby avoiding wiring problems on the chip as well as optimizing each, it is not conducive to rework should modifications or repairs be required. Further, such a method requires development of multi-step processings in order to reliably complete the chip-to-board assembly.